Lateral Double-Diffused (LD) transistors have been widely employed in high voltage applications. One factor which affects the performance of the LD transistors is the drain-to-source on-resistance (Rdson). Higher Rdson undesirably results in reduced switching speeds and more energy loss during switching. Various techniques have been employed to design LD transistors with reduced Rdson. However, conventional LD transistors may be susceptible to the degradation effects associated with hot carrier injection (HCI). For example, impact ionization generated hot carriers may be easily trapped at the silicon and silicon oxide interface regions along the substrate current path. The trapped hot carriers generate defects in the oxide and at the silicon and silicon oxide interface. This compromises device reliability.
From the foregoing, it is desirable to provide reliable low Rdson devices with reduced HCI effects.